In recent years, as the configuration of digital equipment is complicated, it has become desirable to increase the operating speed and performance of a system LSI (Large Scale Integration circuit) which is to be mounted onto the equipment. In particular, high-speed operation of a CPU (Central Processing Unit) which is built into the system LSI has become more desirable than ever.
Typically, in many cases, as a method of operating the CPU at a high speed which would be generally adopted, such a drastic countermeasure as to, for example, increase the number of stages of pipelines that defines the operation of the CPU is taken.
Even when a drastic countermeasure as mentioned above is taken, it may be still desirable that, for example, in setting an access timing between a random logical circuit of the CPU and a cache memory (for example, a primary cache memory) that the CPU itself holds therein, data be read out of the cache memory with no wait in order to increase its throughput.
In addition, as the operating speed of the random logical circuit (an internal logical circuit) in the CPU is increased, it may become desirable to reduce the access time for reading data out of a cache memory (for example, an SRAM: Static Random Access Memory).
Incidentally, nowadays, various memory accessing techniques and information processing techniques for increasing the speed at which a CPU gains access to a memory and various circuits for realizing high-speed data reading out of a cache memory (an SRAM) are proposed.
The operating speed of the CPU (the processing unit) may be further increased by increasing the number of stages of pipelines as described above. However, even if the performance of the logical circuit is improved, it may be difficult to increase the operating speed of the cache memory (the SRAM).
That is, in order to accelerate (increase the operating speed of) the cache memory concerned, it may be desirable to accelerate, for example, the SRAM itself which is used in the cache memory. However, under the current circumstances, it may be difficult to accelerate the SRAM.
In addition, nowadays, for example, the operating speed of the CPU into which the cache memory such as the SRAM is built may become more liable to be controlled by the access time for reading data out of the SRAM and the timing of a data path between the cache memory and the random logical circuit of the CPU.
FIG. 1 is a block diagram illustrating an example of a semiconductor integrated circuit device. 1. FIG. 2 is a diagram illustrating an example of a timing chart for explaining the operation of the semiconductor integrated circuit device illustrated in FIG. 1. Incidentally, the semiconductor integrated circuit device illustrated in FIGS. 1 and 2 is of the type that data is read out of a cache memory with no wait.
In FIG. 1, the example of the semiconductor includes a processing unit (a CPU) 100, a random logical circuit 101, an internal flip-flop 102 and a cache memory 200 (an SRAM).
Incidentally, the cache memory 200 is not limited to, for example, the cache memory of the type which is installed in a semiconductor integrated circuit device such as a system LSI and may be a primary or secondary cache memory which is built into the CPU 100 itself.
As illustrated in the example in FIG. 2, even in the case that data is read out of the cache memory 200 with no wait, an access time ATr which is taken to gain access to the SRAM in one cycle of a clock CLK is increased and a setup margin SMf which is spared for data supply to the next-stage flip-flop 102 is decreased.
Therefore, it may become difficult for the semiconductor integrated circuit device illustrated in FIG. 1 to increase the frequency of the clock CLK and hence it may become also difficult to meet such requirements that the operating speed and performance of, for example, the system LSI into which the CPU is built or digital equipment onto which the system LSI circuit is mounted be increased.
FIG. 3 is a block diagram illustrating another example of the semiconductor integrated circuit device. FIG. 4 is a diagram illustrating a timing chart for explaining the operation of the semiconductor integrated circuit device illustrated in FIG. 3. Incidentally, the semiconductor integrated circuit device which will be explained with reference to FIGS. 3 and 4 is of the type that a flip-flop 300 is provided between the cache memory 200 and the CPU 100.
In the semiconductor integrated circuit device illustrated in FIG. 3, a data path between the cache memory 200 and the random logical circuit 101 of the CPU 100 is once cut off by inserting the flip-flop 300 between them and hence it may be expected to increase the operating speed of the CPU 100.
That is, as illustrated in the example in FIG. 4, owing to the provision of the flip-flop 300, the setup margin SMf which is spared for data supply to the next-stage flip-flop 102 may be increased.
However, in the semiconductor integrated circuit device illustrated in FIG. 3, although the CPU 100 expects to acquire the read data from the cache memory 200 with no wait, arrival of the read data is delayed for a time period corresponding to one cycle owing to the presence of the flip-flop 300.
Therefore, it may be unavoidable to provide a CPU clock control circuit 301 that generates a CPU clk of one cycle from the clock CLK of two cycles so as to operate the CPU 100 at a half-frequency of the frequency of the clock CLK, which may lead to reduction of throughput of the CPU 100.
Specifically, in the case that eight pieces of data have been read out of the cache memory 200 in succession using the CPU 100, the clock CLK of two cycles may be desired every time one piece of data is acquired as will be expressed in the following formula: 8/(8×2)=50%. That is, the performance of the CPU 100 may be reduced by 50%.
The followings are reference documents.    [Document 1] Japanese Laid-open Patent Publication No. 10-333980.    [Document 2] Japanese Laid-open Patent Publication No. 01-276336.